The present invention relates to a data transfer device for transferring plural kinds of data.
Recently, the quantity and kinds of data to be processed by an MPEG decoder or the like have increased and the data processing has become complicated. As a result, there is a need for memories with a large capacity. As such memories with a large capacity, a DRAM, an SDRAM or a RAMBUS-DRAM is used in consumer-oriented electronic products. Such memories have a characteristic that the data transfer efficiency is higher when continuous data accesses are made to continuous addresses than when random accesses are made. In an MPEG decoding process, however, the transfer rate of compressed data, the output rate of image signals and the output rate of audio signals are lower than the memory access rate. Accordingly, when a large quantity of compressed data, image data or audio data in the memory such as a DRAM are accessed at a low rate, the memory transfer efficiency of the memory such as a DRAM is largely lowered. As a countermeasure to improve the memory transfer efficiency, buffer memories for temporarily storing a large quantity of compressed data, image data and audio data are provided in a conventional data transfer device, and when data in a given quantity are stored in each of these buffer memories, the stored data are continuously and rapidly transferred to the memory such as a DRAM.
However, the conventional data transfer device includes the buffer memories respectively corresponding to kinds of a large quantity of data such as compressed data, image data and audio data. Therefore, as the number of kinds of data to be processed is increased, the number of memories to be used is increased, and each kind of data is required to be provided with a data transfer bus, and hence, the area for such buses becomes large. As a result, the entire circuit area becomes disadvantageously large.
As a countermeasure against this disadvantage, a data transfer device including one buffer memory shared between plural kinds of asynchronous data is known. This data transfer device includes data input/output circuits for inputting/outputting respective kinds of data, and these data input/output circuits are assigned access priorities for the shared buffer memory. Thus, the access to the shared buffer memory is successively made in the descending order of the access priorities. In addition, each of the data input/output circuits is provided with a second buffer memory, so that, while data are being input/output between one data input/output circuit and the shared buffer memory, other data can be stored in the second buffer memory of the corresponding data input/output circuit.
However, in this data transfer device, the data input/output circuit having a low access priority cannot make an access to the shared buffer memory within a desired time, and the access within a desired time cannot be guaranteed. Specifically, while the access from a data input/output circuit with a highest access priority is permitted in response to every access request so as to guarantee an access within a desired time, an access request from a data input/output circuit with a lower access priority cannot be permitted when the access request competes with an access request from another data input/output circuit with a higher priority. Thus, an access within a desired time cannot be guaranteed in the data input/output circuit with a lower priority. As a result, it is necessary to use a memory with an unnecessarily large capacity as the second buffer memory of a data input/output circuit having a low access priority.
On the other hand, U.S. Pat. No. 5,533,205 describes a technique regarding access priorities. In this technique, a bus access is divided into a series of time frames, and each time frame is subdivided into smaller time intervals. During selected time intervals, arbitration level indicators associated with particular presentation devices to be used for indicating priorities for the bus access are temporarily reordered to guarantee bus access at a data transfer rate required in each data input/output circuit. However, since the priority for the bus access is changed at small time intervals in this technique, a circuit structure required for the change is complicated.
An object of the invention is providing a data transfer device having a simple structure including one buffer memory shared between plural data input/output circuits, in which transfer of plural kinds of data within desired time periods is guaranteed.
In order to achieve this object, according to the invention, each data input/output circuit is assigned a memory access priority and a memory access request interval.
The data transfer device of this invention comprises plural data input/output means for inputting or outputting data; memory means, serving as a buffer memory, shared by the plural data input/output means for inputting data in or outputting data from the plural data input/output means; and arbitration means for arbitrating access requests for the memory means from the plural data input/output means, wherein each of the plural data input/output means is previously assigned a priority for access to the memory means and is capable of issuing an access request for the memory means at a predetermined time interval, and the arbitration means receives the access requests from the plural data input/output means and gives access permission for the memory means to data input/output means issuing the access requests in the descending order of the priorities.
In one aspect of the data transfer device, the arbitration means gives access permission to data input/output means having a highest priority among the data input/output means issuing the access requests, and each of the data input/output means that is not given the access permission by the arbitration means issues an access request again regardless of the predetermined time interval.
In another aspect of the data transfer device, the arbitration means arbitrates the access requests from the plural data input/output means in every unit access cycle of the memory means.
In still another aspect of the data transfer device, each of the data input/output means includes input means for inputting data; and input data storage means having a capacity sufficient for storing at least data in a quantity input to the input means during a total period including an access request interval for the memory means and a period from issue of the access request to permission of the access request.
In still another aspect of the data transfer device, each of the data input/output means includes output means for outputting data; and output data storage means having a capacity sufficient for storing at least data in a quantity output from the output means during a total period including an access request interval for the memory means and a period from issue of the access request to permission of the access request.
In this manner, according to the present invention, in the plural data input/output means sharing one memory means, time intervals of access requests for the shared memory means from the respective data input/output means are set to be predetermined intervals. Therefore, each of the data input/output means is guaranteed to definitely make an access to the shared memory means within a desired time period. Accordingly, the capacities of second buffer memories included in the respective data input/output means can be previously definitely grasped. As a result, the capacities of the second buffer memories can be decreased as compared with those in the conventional technique.
In particular, when the arbitration of the access requests from the data input/output means is conducted in every unit access cycle of the memory means, the capacities of the second buffer memories of the respective data input/output means can be suppressed to necessary minimum capacities.
Furthermore, the data storage capacity of each data input/output means can be definitely determined as the capacity for storing at least data in a quantity input/output during the total period including the access request interval for the memory means and the period from issue of the access request to the permission of the access request.